1. Field of Invention
The invention relates to a method of designing the control signal circuits in a memory, particularly to a method of designing a control signal circuit that is used to perform buffer access in a printer, and is able to control the access pointers according to the transfer mode and improve the buffer processing efficiency in sequential mode when printing.
2. Related Art
Since the computing power of computer-based devices is more than that of printing peripherals (e.g., printers), printing peripherals usually employ several data buffering mechanisms to coordinate the unmatched data transfer speed and computing power between them.
Data buffering mechanisms usually consist of two parts: one is the control signal circuit and the other is the memory. Suppose that a memory consists of four memory blocks and each memory block consists of eight registers. These memory registers can be accessed in different transfer modes (parallel mode or sequential mode) and access modes (read mode or write mode) according to the control signal circuit. In data accessing in parallel mode (shown in FIG. 1-a) and sequential mode (shown in FIG. 1-b), after receiving a control signal, the prior control signal circuit can only control the access pointers by sending a prior read control signal 100 or a prior write control signal. As shown in FIG. 1-a, in parallel mode, four memory blocks can be accessed simultaneously by a read pointer 110 and a write pointer 220. However, as shown in FIG. 1-b, in sequential mode, only one memory block can be accessed at a time with the same access pointers (i.e., the read pointer 110 and the write pointer 220). The design of the control signal circuit has the limitation that the other three memory blocks cannot be accessed as long as one memory block is accessed.
As a result, in sequential mode, the prior designs of the control signal circuits waste a large amount of memory space, and degrade the efficiency of data buffering. It is because of their the bad designs that the control signal circuits cannot manipulate the control signals and access pointers well, and hence, waste memory space and are inefficient in data buffering. In addition, the prior designs limit the arrangement of the memory block and are not able to fulfill the requirements of data buffering. As a consequence, improving the design of the control signal circuits to increase the efficiency of data buffering especially in sequential mode is a crucial issue for control signal circuit designers.